1. Field of the Invention
The present invention relates to a sensing current reduction device for a semiconductor memory device, and a method therefor, and in particular to an improved sensing current reduction device for a semiconductor memory device which can reduce a sensing current occupying a great part of an operating current and consume less power, by controlling a bit line sense amplifier to be operated after receiving a column address, and a method therefor.
2. Description of the Background Art
In general, a dynamic random access memory (DRAM) consumes much power, as compared with other memory devices, such as a static random access memory (SRAM). It is because the DRAM cell must perform a refresh operation.
That is, as the time elapses, data stored in a capacitor constituting the memory cell are lost with a leakage current. Accordingly, a process for sensing and restoring the data is necessary before the data are lost. In addition to the refresh operation, mostly in the DRAM operation, word lines of the memory cells more than those storing the externally-required data are enabled, thereby performing a sensing operation.
As described above, the sensing operation of the memory cells is not necessary, except for a pull-page operation. All the memory cells are written again according to a refresh command before the data are lost. Therefore, in a general read operation, if the data of the memory cell did not required, the sensing operation about the memory cell is consumptive.
Accordingly, in order to reduce the current consumption, it is essential to minimize the number of the cells wherein the word lines are opened and the sensing operation is necessary in a row active operation.
For example, the case that the number of the cells is 64M (64.times.1024.times.102=2.sup.26) will now be explained.
In this case, addresses of 26 bits are necessary in order to select one of the cells. However, most of the DRAM devices which have been manufactured and distributed input/output four, eight or sixteen data at the same time, instead of inputting/outputting the data one by one. Thus, it is not necessary to divide the addresses of the data groups (four, eight and sixteen). As a result, addresses of smaller bits than 26 bits are required. When the products are named .times.4, .times.8 and .times.16 products, respectively, the 64M(.times.4) product needs addresses of 24 bits, the 64M(.times.8) product needs addresses of 23 bits, and the 64M(.times.16) product needs addresses of 22 bits.
A conventional method for the DRAM device to receive the addresses inside will now be described.
The DRAM device does not receive the addresses at one time. That is, the DRAM device receives the addresses inside according to an address multiplexing method, which has been designated as the Specification in the relational field.
So long as a completely new DRAM device is not developed and deemed to have applicability, and the Specification is separately designated, all the DRAM devices generally employ the address multiplexing method.
The address multiplexing method is to receive the addresses for selecting the cell in twice. Here, only a half of address pins are required, as compared with other methods which do not use the address multiplexing method.
Accordingly, the address multiplexing method has many advantages in that the number of pins and pads reduces, and that the number of circuits such as an input buffer also decreases.
The address which is firstly inputted in the address multiplexing is called a row address. The word line is selected by utilizing the row address, and a bit line sense amplifier is operated, waiting for a column address which will be a second address.
However, once the word line is selected and opened, electric charges (indicating the data of `1` and `0`) stored in the cell flow into bit lines BL, /BL, and thus the a charge sharing is performed. Accordingly, it is required to sensing and restoring the data before closing the word line. As a result, the sensing operation is necessary.
Therefore, the number of the cells opened by the word line is determined by the number of the row addresses which are firstly inputted. After finishing the aforementioned step, the column address signal which is the second address is inputted. Thus, the group of the cells (four, eight and sixteen) sensed after enabling the word line can be selected by decoding the column address.
As known from the above-described address multiplexing method, in order to reduce the current consumption, a smaller number of word lines must be enabled, and thus a smaller number of cells must be opened and sensed. The limit is determined by the number of the row addresses. It cannot be overcome according to the method for opening the cell by enabling the word line before receiving the column address.
That is to say, in the case that the cells are opened fewer than the cells which can be opened by the row addresses according to the aforementioned limit, when the necessary cell is selected by using a succeeding column address signal, the cell which is not opened may be selected.
In this regard, the 64M DRAM product will now be exemplified.
According to the Spec., the 64M DRAM product must be provided with fourteen address pins A0-A13. In addition, in the case of the 64M(.times.4) DRAM, the number of the cells to be selected is 2.sup.24. When it is presumed that the row address signals inputted at an initial stage are maximally 14 bits ax0.about.ax13, if 2.sup.14 cells are selected by using the row address signals of 14 bits, the number of the cells which are not selected is 2.sup.10. In the case of the .times.4 product, 2.sup.12, namely 4k cells remain.
That is, 2.sup.14 cells are firstly selected among the whole 64M cells by the row address signals of 14 bits firstly inputted according to the address multiplexing method, and the residual 4k cells wait for being selected by column address signals of 10 bits ay0.about.ay9. Here, the state of waiting for selection implies a state where the 4k cells are opened by the word lines and sensed by the bit line sense amplifier.
In case the DRAM is designed so that the cells fewer than 4k can wait for being selected by the column address, as described above, when a specific column address is selected, the cell may not be opened. In this case, the data of the cell cannot be read or write.
Accordingly, the 4k cells must be opened in the 64M (.times.4) DRAM product.
That is, when it is presumed that the number of the cells to be selected is 2.sup.n, and the number of the address pins available is 2.sup.m, in accordance with the method for opening the cell by enabling the word line before receiving the column address signal, at least 2.sup.n-m cells must be sensed. As a result, the sensing current occupying a most part of an operating current in the DRAM operation is much consumed, thereby increasing the current consumption of the whole device.